Job Id: 20201108009
Job Role: DFT CAD Developement -Sr.Engg
Experience: 3-10 Years
Qualification: Bachelor’s or Masters degree in Engineering
Job Location: Noida
Salary: Best in Industry
Vacancies: Not Mentioned
Job Description Qualcomm Noida Jobs for DFT CAD Developement Engineer in November 2020:
As a person hired into this role you will be Define, Develop and Deploy DFT CAD Solutions in the areas of DFT Implementation, Test Vector Generation and Silicon Bringup. We believe in fast paced development, Innovation and partnership across teams and sites to deliver CAD Solutions to enable Best In Class Chipsets for a Connected world.
You will design, develop, deploy and support innovative Products, Methodology and Flows to enable Implementation, integration and verification of DFT logic designs at block/IP level and chip level while minimizing DFT impact on schedule, timing, area, and power. You are expected to participate in all aspects of software development with enthusiasm: collecting requirements, writing specifications, coding, testing and supporting customers.
Plan and implement tool flows to meet test requirements for high volume manufacturing, including at-speed scan test with compression, Logic BIST, Memory BIST, and boundary scan, while utilizing industry standards Create flows/methods to enable timing constraints for all DFT modes and collaborate with physical design teams to close timing and physical design signoff requirements.
Enable automation to generate production quality manufacturing test patterns, and assist with bring-up and debug on Automated Test Equipment (ATE).
Providing tool and flow training to design engineers Evaluate and Qualify DFT tools and Working with EDA vendors on resolution of tool and flow issues
A bachelor’s or Masters degree in Engineering with 3-10 years of professional work experience in the area of DFT CAD Development
Programming Expertise with C,C++,Perl, Python
Strong abstraction and algorithmic skills.
Experience of working with a large code base.
Experience with Flow Architecture and Tool design and Development.
Knowledge of DFT concepts
Ability to work in an international team, dynamic environment
Ability to learn and adapt to new tools and methodologies.
Ability to do multi-tasking & work on several high priority projects in parallel.
Excellent problem solving skills
Excellent communication and team work skills and good English is required
Knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis
Knowledge and hands on experience in MBIST insertion and Memory test validation
Knowledge in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations
Experience in RTL and Gate level simulations of scan and MBIST test vectors
Working Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TetraMax)
Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus