Senior ASIC Design Engineer – Hardware
What you will be doing:
Collaborate with technology leads, circuits and systems teams, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance.
Understand corner case timing sign-off risks in the latest 5nm and deeper technology nodes. Develop strategies to mitigate and margin for them.
Develop tools and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer.
Extensively work with our ASIC Physical Design team to help develop methodologies, flows, and tools across a wide spectrum of domains – STA, constraints, floorplanning, timing and power optimization.
What we need to see:
Master’s Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent work experience
At least 3+ years of relevant work experience
Deep understanding of backend design process, especially advanced STA.
In depth understanding of PT and/or Tempus
Expertise in coding — TCL, Perl, Python. C++ is a plus!
Strong communication and interpersonal skills
Ways to stand out from the crowd:
Expertise in developing advanced STA flows
Location: Bangalore, Hyderabad