Electrical Engineer Jobs in Bangalore – Nuvia Hiring For DV-SOC-DFX Verification

Job Id: 20200731011

Company: Nuvia

Job Role: DV – SOC – DFX Verification

Experience: 7+ Years

Qualification: BA/BS degree in Electrical Engineering

Job Location: Bangalore

Salary: Best in Industry

Vacancies: Not Mentioned

Website: www.nuvia.com

Job Description Nuvia Electrical Engineer Jobs in Bangalore Hiring For DV-SOC-DFX Verification in July 2020:

As a SOC DV Engineer with a focus on DFD and DFT feature verification, you will work to understand the internal requirements and complexities of our SOC system and architect the required verification strategy. You will help set up methodologies, come up with test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle.

Minimum qualifications
BA/BS degree in Electrical Engineering with 7+ years of practical experience
Strong fundamentals in digital ASIC verification
Experience with ARM Coresight architecture and implementation
Experience with verification SOC debug units like PMU, ETM, ELA, DAP, ATB, STM, etc.
Experience in verification of debug and trace features at SOC and SS level
Strong understanding of IO interfaces for debug like JTAG, SWD, HSIF, USB etc.
Strong understanding of debug SW tool chains
Experience in various aspects of DFT verification- SCAN , ATPG , BSCAN, MBIST
Strong programmable language experience is required (one or more of Verilog, SystemVerilog, Perl, Python, Tcl Scripts, Makefile and/or C++)

Preferred qualifications
MS degree in Electrical Engineering; 10+ years of practical experience
Prior experience in developing methodology for functional vector generation and debug for ATE
Expertise in the verification of ARM based CPU SS verification [ SMMU , GIC , Fabric etc ]
Strong understanding of AMBA bus protocols
A good understanding of the complete verification life cycle (test plan, testbench through coverage closure)
Extensive knowledge in multiple testbench structures
Knowledge of FPGA and emulation platforms
Proficiency in UVM, C/C++
Experience w/ PSS or higher level test construction languages
Knowledge of assertion-based formal verification

Roles and Responsibilities
Define entire verification architecture for all system boot flow aspects
Deep dive into microarchitecture of all agents and subsystems involved with system boot flows
Define verification architecture, develop test plans and build verification environment
Work with design team to understand design intent and bring up verification plans and schedules
Verify Subsystems and Full SoC using advanced verification methodologies
Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard
Debug test cases and report verification result to achieve expected code/functional coverage goal
Assist in emulation, FPGA, prototyping efforts
Assist in silicon bring-up, debug and characterization

Apply for Nuvia Electrical Engineer Jobs in Bangalore Hiring For DV-SOC-DFX Verification in July 2020:

Off campus Drives

Leave a Reply

Your email address will not be published. Required fields are marked *

%d bloggers like this: