Job Id: 20201011006
Company: Microchip Technology
Job Role: Pr. Engineer-ASIC Design
Experience: 10 Years
Qualification: Bachelors/Master’s in electrical engineering, Computer Engineering or Computer Science.
Job Location: Hyderabad
Salary: Best in Industry
Vacancies: Not Mentioned
Job Description Microchip Careers Electrical Engineer Job Vacancies for ASIC Design Engineer in October 2020:
Minimum of 10 years of proven silicon design experience in high speed RTL design of DDR Memory Controllers, PHYs, QDR Memory Controllers or other related logic.
Duties & Responsibilities
General RTL and ASIC development
Detailed module design, performance analysis and detailed design specification creation
Participate in the RTL implementation, synthesis, formality check as well as ECOs
Support post-layout timing closure and verification
Participate in the investigation & assessment of emerging Memory Interface technologies & IPs
Improve Data & Command processing bandwidth, reduce latencies & increase reliability
Support porting the design into test chips and emulation platforms
Support pre-tapeout verification and post-tapeout validation/characterization of the system designed
Work closely with FPGA support software and FW engineers to resolve hardware issues and customer issues
DDR Memory Controller / PHY Development
Integrate DDR Memory Controller Logic into a final design, including resets, clock domain crossing, power-down controls, calibration logic, and associated register maps.
Work with 3rd party vendors for evaluation of potential IP cores and work with those IP providers to ensure robust, high bandwidth solutions.
Develop Block Level Constraints and run synthesis
Perform Static Timing Analysis of the Memory Controller and PHY digital logic and review post-layout timing.
Support Verification and Validation groups in testing of the DDR Memory Controller and other similar logic blocks.
Integrate and simulate memory controller designs including
Integration into processor sub-systems as needed.
Integration into IP used in the FPGA fabric of the device
Develop and/or integrate to industry standard Memory Controller Protocols
DDR5, DDR4, LPDDR5, LPDDR4, DDR3, GDDR6, etc.
Support for stand-alone components or DIMMs
Fully embedded solutions such as HBM are a plus
Ongoing customer support to ensure the Memory Controller/PHY is robust with performance that meets the customer performance and/or power goals.
Support RTL design engineers with less experience for the functions shown above
Experience is SOC IP development for Memory Controllers and associated protocols
Strong Experience in RTL design, design verification, synthesis & formality
Strong Experience in Static Timing Analysis and Verilog simulation tools
Should be able to design complex state machines & data path logic
Ability to write detailed design specifications
Good analytical, oral and written communication skills
Able to write clean, readable presentations.
Self-motivated, proactive team player.
Ability to work to schedule requirements.
FPGA and ASIC System On Chip Design Experience
Lab Experience for System Level Validation